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Espressif Systems /ESP32-S3 /PCNT /U0_CONF0

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Interpret as U0_CONF0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FILTER_THRES0 (FILTER_EN)FILTER_EN 0 (THR_ZERO_EN)THR_ZERO_EN 0 (THR_H_LIM_EN)THR_H_LIM_EN 0 (THR_L_LIM_EN)THR_L_LIM_EN 0 (THR_THRES0_EN)THR_THRES0_EN 0 (THR_THRES1_EN)THR_THRES1_EN 0CH0_NEG_MODE 0CH0_POS_MODE 0CH0_HCTRL_MODE 0CH0_LCTRL_MODE 0CH1_NEG_MODE 0CH1_POS_MODE 0CH1_HCTRL_MODE 0CH1_LCTRL_MODE

Description

Configuration register 0 for unit 0

Fields

FILTER_THRES

This sets the maximum threshold, in APB_CLK cycles, for the filter.

Any pulses with width less than this will be ignored when the filter is enabled.
FILTER_EN

This is the enable bit for unit %s’s input filter.
THR_ZERO_EN

This is the enable bit for unit %s’s zero comparator.
THR_H_LIM_EN

This is the enable bit for unit %s’s thr_h_lim comparator.
THR_L_LIM_EN

This is the enable bit for unit %s’s thr_l_lim comparator.
THR_THRES0_EN

This is the enable bit for unit %s’s thres0 comparator.
THR_THRES1_EN

This is the enable bit for unit %s’s thres1 comparator.
CH0_NEG_MODE

This register sets the behavior when the signal input of channel 0 detects a negative edge.

1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
CH0_POS_MODE

This register sets the behavior when the signal input of channel 0 detects a positive edge.

1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
CH0_HCTRL_MODE

This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.

0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification
CH0_LCTRL_MODE

This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.

0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification
CH1_NEG_MODE

This register sets the behavior when the signal input of channel 1 detects a negative edge.

1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
CH1_POS_MODE

This register sets the behavior when the signal input of channel 1 detects a positive edge.

1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
CH1_HCTRL_MODE

This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.

0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification
CH1_LCTRL_MODE

This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.

0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data